Due to higher frequencies at which semiconductor integrated circuits (ICs) operate, IC designers are confronted with smaller or tighter operating windows. For example, in memory ICs such as dynamic random access memories (DRAMs), it is becoming more difficult to perform certain operations such as reads, writes, or precharges within a chip's cycle time. An aspect that limits the speed of operations in memory ICs is the charging of bus lines. For example, there are buses that need to be charged to an appropriate level within a clock cycle. Clocking the operation of ICs is a well-established concept. Higher operating frequencies make it increasingly difficult for a driver circuit to charge buses within the given clock cycle.
The inability of the charge circuitry to charge the buses within the given time may require a modification in the chip's operational specification. For example, a DRAM may require a wait cycle after a write operation before a read operation can be performed. However, such a solution is undesirable as it impairs performance.
A conventional technique for improving the performance of the driver is to increase the voltage to which the driver charges the load. This produces an increase in the differential or voltage swing between the logic high and logic low voltage levels. The larger voltage swing between the high and low levels requires a greater amount of time to charge and discharge, for example, the buses, causing a degradation in performance. Additionally, increasing the voltage increases the power consumption, which is undesirable, particularly with portable systems such as laptop computers.
As evidenced by the above discussion, it is desirable to provide an improved driver circuit with an increase in charge rate that allows for faster operation of ICs.